The present invention relates to integrated circuits and, more particularly, to electrically configurable integrated circuits. A major objective of the present invention is to provide for slave serial mode programming of electrically configurable integrated circuits using a reduced pin count.
Much of modern progress is associated with the increasing functionality and speed of integrated circuits. When produced in large quantities, integrated circuits are sufficiently inexpensive that computers, instruments, and consumer products incorporating them are within the reach of everyone. However, very high start-up costs, including research, manufacturing facilities, design, processing, and testing, can be prohibitive, for small volume applications. Low volume runs are important, not only for certain specialized applications, but as intermediate steps in the development of integrated circuits eventually destined for large volume production.
Various "application-specific integrated circuit" (ASIC) technologies have addressed the problem of start-up costs. However, because they involve reliance on further manufacturing to realize a design, start-up costs are higher than desired for many applications.
Where the desired functionality can be achieved, programmable devices afford a very attractive approach to small volume integrated circuit manufacturing. The functionality of programmable devices is determined after they are, manufactured, typically by selecting binary values to be stored in included configuration memory cells. The most basic programmable device is a programmable read-only memory (PROM). Programming a PROM determines what data will be output for each of its memory addresses.
Programmable device designs can be updated by device replacement. Electrically configurable devices (ECDs) can be updated by erasing the old configuration and programming a new configuration without replacing the integrated circuit. ECD devices can be memories, e.g., electrically-erasable programmable read-only memories (EEPROMS), and logic devices, e.g., electrically programmable logic devices (EPLDs), including electrically programmable gate arrays (EPGAs) The advantages of electrically configurable devices during iterative design stages is clear. Their flexibility for improvements has made such devices attractive even in high volume applications.
Most EPGAs have multiple programming modes. In master modes, the EPGA controls the timing and addressing of data to be loaded. A serial master mode provides for serial data transfers; a parallel master mode provides for parallel data transfers. Parallel data transfers can also be conducted in a peripheral mode, in which the EPGA is treated as a peripheral, supplied with a clock. In a slave serial mode, serial data is presented in parallel with a synchronizing clock signal to the EPGA. Slave serial mode is often used in conjunction with master and peripheral modes as slave EPGAs are daisy chained to a master EPGA for progressive programming. Slave serial mode typically requires three pins for programming. One pin is to indicate that programming is active, a second pin presents data, and a third pin provides the synchronizing clock.
One challenge shared by many integrated circuits is to provide sufficient interfacing capabilities to take advantage of the functionality and performance capabilities afforded by advancing integrated circuit technology. Pin count, the number of pins for interfacing an integrated circuit package with a host system, serves as a measure of interfacing capability. Pin count has not been able to keep pace with increasing circuit density for several reasons. It is difficult to reduce the package area consumed by a pin. In addition, significant integrated circuit area is required for bonding pads for electrically coupling pins and circuit elements. In addition, the area consumed by circuitry for buffering integrated circuit inputs and outputs is substantially greater than that required by core circuit elements.
Competition among circuit functions for pins is aggravated in the case of electrically erasable programmable devices, since pins are required for configuration as well as for operation of the configured device. To some extent, the pin count can be reduced by assigning to the same pin one function during programming and another function during normal operation. However, this dual-use approach risks interface contentions in a host system; addressing this risk increases the burden on and the costs to the designer of the incorporating system.
What is needed is an EPGA system that provides for reduced pin counts and/or reduced requirements for pins used for programming. Preferably, the reductions are accomplished without substantially affecting device performance.